Optical lithography is a process using light, such as ultra-violet (UV) light, to transfer a pattern associated with an integrated circuit (IC) design from a lithographic mask, reticle, or both, to a layer of photoresist material that has been deposited on a surface of a semiconductor wafer. Either the exposed portion of the photoresist material or the unexposed photoresist material is removed, thereby enabling further fabrication of the IC design. Typically, multiple layers are involved in the fabrication of an IC. As the semiconductor industry continues to push toward smaller device geometries, the wavelength of light used in the lithographic process may be on the order of the linewidths used in the IC design. Therefore, optical distortions of the transferred pattern may occur. Further, manufacturing process effects may cause additional distortions in the fabrication of the IC.
Optical proximity correction (OPC) is a technique used to compensate for optical distortions, process effects, or both, by modifying or correcting the pattern that is used during lithography. There are at least two types of OPC, which may include rule based OPC and model based OPC. In rule based OPC, experiments are used to determine the corrections that are needed to compensate for the non-ideal effects of the lithography system and the manufacturing process. Unlike rule based OPC, model based OPC uses simulations, typically in an iterative manner to determine the OPC needed for a specific IC design. A reference OPC model, which may include an optical model, a resist model, other process effects models, or any combination thereof, is created for a specific process technology and used in a fabrication simulation to simulate the distortions that a desired design layout pattern undergoes during the lithography process, the manufacturing process, or both. Additionally, the reference OPC model is used to create an OPC design layout pattern based on pre-distorting the desired design layout pattern, such that when the IC is produced, the OPC design layout pattern provides a fabricated IC that ideally matches the desired design layout pattern.
The desired design layout pattern is made up of multiple polygons. The OPC design layout pattern is created by fragmenting the polygons of the desired design layout pattern and moving the fragments to create necessary pre-distortions of the desired design layout pattern. The reference OPC model typically uses many iterations to create an OPC design layout pattern. The reference OPC model begins by applying initial fragment movements to the desired design layout pattern to create an initial OPC design layout pattern. The initial OPC design layout pattern is then fed into the fabrication simulation. The results of the fabrication simulation are compared to the desired design layout pattern. If necessary, additional fragment movements are applied to the initial OPC design layout pattern to create another OPC design layout pattern, which is then fed into the fabrication simulation. This process is repeated until the results of the fabrication simulation nearly match the desired design layout pattern. The number of iterations to create an OPC design layout pattern is based on how close the initial fragment movements are to the needed fragment movements in the OPC design layout pattern and how quickly the iterative fragment movements converge on the needed fragment movements.
The fabrication simulation may be very complex for large IC designs and thousands of fragment movements may be necessary for each iteration. Additionally, large IC designs may require many iterations. Therefore, the computation time for a large IC design may take days. Since computation time for an IC design is about proportional to the number of iterations needed to create a final OPC design layout pattern, and since the number of iterations is based on how close the initial fragment movements are to the needed fragment movements in the OPC design layout pattern, the computation time for an IC design may be significantly reduced if the initial fragment movements are close to the needed fragment movements in the OPC design layout pattern. Thus, there is a necessity to determine initial fragment movements that are close to the needed fragment movements.